Output buffers are commonly used in memory devices, such as dynamic random access memories (“DRAMs”), to supply data from a location in a memory array to one or more data bit terminals of the memory device during a memory read operation. The data bit terminal is commonly referred to as the “DQ” terminal. When a memory location storing a value of logic “1” is read, the output buffer receives complimentary logic “1” and logic “0” signals at respective DATA and DATA* input terminals and applies a logic “1” signal (which may be 3.3 volts or 5 volts, for example) to the DQ terminal. When a memory location storing a value of logic “0” is read from a memory location, the output buffer receives complimentary logic “0” and logic “1” signals at respective DATA and DATA* input terminals and applies a logic “0” signal to the DQ line. Although the prior art output buffers will be described as being a component of a DRAM, it will be understood that they are also used in devices other than DRAMs, such as in static random access memories (“SRAMs”).
As output buffers have developed in speed and capability, they have been designed to perform additional functions. One of these functions is a data mask operation in which the data output terminal of the output buffer is switched to a high impedance or “tri-state” condition responsive to a data mask signal, known as a “DQM” signal. During this tri-state condition, the output buffer does not output any signal at the DQ terminal.
The conventional approach to masking a data signal output by a data output buffer is to apply the DQM signal to an active low enable input of an output buffer 10, as illustrated in FIG. 1. The DQM signal is applied to the enable output buffer 10 through a register 12 that is enabled by a clock (“CLK”) signal. Thus, the DQM signal is registered to the edge of the CLK signal, although the DQM signal may be delayed to some degree in being coupled out of the register 12 to the output buffer 10. Similar, and often longer, delays may occur in coupling the DATA and DATA* signals to the output buffer 10.
During a normal read operation, the DQM signal is a logic “0” thereby enabling the output buffer 10. As a result, the output buffer 10 applies a data output signal to the DQ terminal that correspond to the complimentary DATA and DATA* inputs to the output buffer 10.
With reference to FIG. 2, when a masked data read operation is to occur, a logic “1” DQM signal is applied to the enable input of the output buffer 10. As is conventional, the output buffer operates with a read latency, which may be 2 clock cycles as shown in FIG. 2. In a latency of 2, an active DQM signal is applied to the output buffer 10 approximately 2 clock pulses before the data to be masked are applied to the DATA and DATA* input of the output buffer 10. Thus, the output buffer 10 is disabled approximately 2 clock pulses after DQM goes high. As a result, the output buffer 10 passes the first two bits of data, but its output is tri-stated during the third bit of data. Thus, during the time that DATA2 and DATA2* are applied to the output buffer 10 and the output buffer would otherwise output a corresponding DQ signal on the DQ terminals of the output buffer 10, the DQ terminal of the output buffer 10 becomes essentially open circuited. (The DATA* signal has been omitted from FIG. 2 since it is simply the compliment of DATA).
The above-described conventional approach to performing a masked data read operation is satisfactory if the DQM signal is properly synchronized with the DATA and DATA* signals. Under these circumstances, the output buffer 10 is disabled as illustrated in FIG. 2 in a manner in which the entire DATA2 signal is masked, but no part of either DATA1 or DATA3 is masked. However, in practice, particularly at higher operating speeds, the DQM signal is often not well synchronized to the DATA and DATA* signals. If an active high DQM signal is applied to the output buffer 10 too late relative to the DATA and DATA* signals, then the trailing part of the data bit prior to the desired data bit will be masked, and the trailing part of the desired data bit will not be masked. With reference to FIG. 3, the output buffer 10 is disabled after the DQM signal goes high with the same latency delay shown in FIG. 2. However, the DATA and DATA* signals are applied to the output buffer 10 later than as shown in FIG. 2. As a result, the trailing portion of the DQ1 bit is improperly masked, and the trailing portion of the DQ2 bit is improperly not masked. Under these circumstances, the DQ1 bit may be present for less than the output hold time tOH specified for a memory device using the output buffer 10. Furthermore, the output buffer 10 may fail to mask the DQ2 bit so that it is read by a processor (not shown) or other device performing the read operation. Although the problem illustrated in FIG. 3 has occurred because of an excessive delay in applying the DATA and DATA* signals to the output buffer 10, the same problem occurs if the DQM signal is applied with insufficient delay (i.e. to early), or any combination of the DATA and DATA* signals applied too late and the DQM signal applied too early.
A problem similar to that illustrated in FIG. 3 occurs if the DQM signal is applied to the output buffer 10 too late, the DATA and DATA* signals are applied to early, or any combination of the two. With reference to FIG. 4, the output buffer 10 is once again disabled after the DQM signal goes high with the same latency delay shown in FIGS. 2 and 3. However, the DATA and DATA* signals are applied to the output buffer 10 earlier than as shown in FIG. 2. As a result, the leading portion of the DQ2 bit is improperly not masked, and the leading portion of the DQ3 bit is improperly masked. Under these circumstances, the DQ3 bit may be present for less than the output hold time tOH specified for a memory device using the output buffer 10. Furthermore, the output buffer 10 may once again fail to mask the DQ2 bit so that it is read by a processor (not shown) or other device performing the read operation.
Although both of the above-described problems could theoretically be solved by precisely synchronizing the DQM signal to the DATA and DATA* signals as they are applied to the output buffer 10, in practice it is not possible to synchronize the signals to each other with adequate precision. Furthermore, the delays are difficult to predict and may vary with time with different memory devices and with different systems using the memory devices, thus making it impractical to synchronize the signal to each other by imposing a compensating delay on either the DQM signal or the DATA and DATA* signals. There is thus a need for an output buffer that is capable of precisely masking the entire portion of a desired data bit without masking any portion of adjacent data bits.